FiLabs joins OpenForge as design partner for ComputeFi silicon

Future Intelligence Labs, Inc. said June 9 it has partnered with OpenForge to support the design pillar of Cysic’s ComputeFi hardware coalition. The move is aimed at speeding development of ZK and AI inference chips by using AI-native chip design to cut time and cost.

Why it matters: - OpenForge is trying to compress the time and cost needed to build purpose-built silicon for verifiable compute. - The partnership targets workloads tied to zero-knowledge proof generation and verifiable AI inference, two areas where demand is rising across rollups, decentralized applications and AI systems. - FiLabs says its approach could reduce a key bottleneck in ASIC development: long timelines and high upfront engineering spend.

What happened: - Future Intelligence Labs, Inc. (FiLabs) announced a strategic partnership with OpenForge on June 9, 2026. - FiLabs joined OpenForge as a partner in its design pillar. - The work will focus on next-generation hardware for zero-knowledge proof generation and verifiable AI inference. - OpenForge is the vertically integrated hardware coalition behind Cysic’s ComputeFi thesis.

The details: - FiLabs is an AI-native chip design house that uses multi-agent AI to handle RTL, verification and physical layout. - Conventional ASIC design houses typically need 12 to 18 months and $10 million to $25 million in non-recurring engineering costs per program. - FiLabs says early engagements have delivered up to 150x design-efficiency gains, 100% verification coverage on delivered modules and timelines cut by about 50% at one-third the cost. - The company says those results can compress critical design stages from months to weeks while maintaining production-grade rigor. - The partnership will start with design exploration and verification for a next-generation ZK accelerator. - The scope may expand to AI inference ASICs and the portable ZK Air form factor. - Dr. Leo Fan, founder and CEO of Cysic, said OpenForge is intended to assemble the silicon supply chain across design, manufacturing and distribution. - Dr. Meng, CEO of FiLabs, said cryptographic silicon is a strong fit for the company’s model because the workload is complex, high-stakes and underserved by legacy design houses. - FiLabs’ website is More information. - OpenForge’s website is More information. - Cysic’s website is More information.

Between the lines: - OpenForge is betting that AI-native chip design can change the economics of ASIC development, not just improve execution. - The partnership also signals that Cysic wants tighter coordination across the full hardware stack instead of traditional serial handoffs. - If FiLabs can reproduce its claimed speed and cost gains on cryptographic silicon, it could help lower the barrier to building specialized compute hardware.

What's next: - The first phase will center on design exploration and verification. - Any expansion into broader silicon programs will likely depend on how the ZK accelerator work performs. - OpenForge and FiLabs could extend the relationship into additional accelerator and AI inference projects if the initial engagement scales as planned.

The bottom line: - FiLabs becomes OpenForge’s first AI-native chip design partner, and both companies are positioning the deal as a way to make verifiable compute faster, cheaper and more scalable.